Research5 min read

What does “2 nm” actually measure?

The newest chips are sold as “2 nm”, but nothing inside them is 2 nm wide. The number names a generation of manufacturing, and it has not been a measurement for about thirty years.

The chips in this year’s newest phones, laptops and AI servers are described with one short number: 2 nm. It reads like a measurement. A nanometre is a billionth of a metre, so you might picture a transistor just 2 nm wide.

Nothing on a “2 nm” chip is 2 nm wide in that sense. The number is a name for a generation of manufacturing technology, called a process node. It started as a measurement and slowly became a label.

When the name was a measurement

Until the mid-1990s, the node name described something real. A 0.35 µm process could draw lines about 0.35 µm wide, and that set the length of the transistor’s gate, the part that switches current on and off.

After that, the name and the physical sizes went separate ways. By 2001, Intel’s “130 nm” chips had gates only about 70 nm long. Each new generation was still named about 0.7 times the previous one, because shrinking a transistor by 0.7 in both directions halves its area, so the names kept falling on schedule whatever the real sizes did.

What engineers measure instead

Today’s transistors are 3D structures, so there is no single size to quote. Engineers describe a process by how closely things can be packed, and two numbers matter most. The gate pitch is the distance from one transistor gate to the next. The metal pitch is the distance between the thinnest copper wires that connect the transistors.

Top-down sketch of transistors and wires Vertical gate lines cross horizontal channels. The gate pitch is the distance between two neighbouring gates. Above the transistors, copper wires are spaced by the metal pitch. gate pitch transistors: gates (copper) across channels (grey) metal pitch copper wiring above them
Figure 1. The two spacings that describe a modern chip process. Sketch, not to scale.

The numbers behind the names

TSMC’s “7 nm” process has a gate pitch of 57 nm. Its “2 nm” process, in mass production since late 2025, reportedly has a gate pitch of about 48 nm. Intel’s newest process is called “18A”, meaning 18 ångströms or 1.8 nm, and Intel gives its gate pitch as 50 nm.

Node name compared with real pitches TSMC N7: name 7, gate pitch 57, metal pitch 40 nanometres. TSMC N2: name 2, gate pitch about 48, metal pitch about 26. Intel 18A: name 1.8, gate pitch 50, metal pitch 32. 01020 30405060 nm 7 57 40 TSMC “7 nm” 2 ~48 ~26 TSMC “2 nm”* 1.8 50 32 Intel “18A” name gate pitch metal pitch
Figure 2. From “7 nm” to “2 nm” the name shrinks by more than two thirds. The gate pitch shrinks by less than a fifth. *Reported figures; TSMC has not published them.

The names don’t even line up between companies. Intel’s old “10 nm” process packed transistors about as tightly as TSMC’s “7 nm”. In 2021 Intel renamed its processes: the improved 10 nm became “Intel 7”, and the one after it “Intel 4”. Intel said the new names would compare more clearly with the rest of the industry. Nothing on the chips changed size.

Why it can’t be literal

Silicon is a crystal, and its repeating unit is about 0.54 nm wide. So 2 nm is less than four of those units. A working transistor needs a gate, contacts and insulation between them, and that does not fit in so few. At those distances electrons would also slip straight through the barriers that are meant to stop them.

2 nm compared with a 48 nm gate pitch, drawn in silicon crystal units A row of 88 dots, each one silicon crystal unit of 0.54 nanometres, spans a 48 nanometre gate pitch. A bracket shows that 2 nanometres covers less than four of them. 2 nm 48 nm: the gate pitch of a “2 nm” chip each dot is one silicon crystal unit, 0.54 nm
Figure 3. Drawn to scale. The name “2 nm” covers fewer than four crystal units. The space between two neighbouring gates covers 88.

Is it all marketing?

Each new node is still a real improvement. TSMC says its 2 nm process packs logic about 15% more densely than its 3 nm process and can run up to 30% more efficiently. Most of that gain now comes from new transistor shapes, such as the stacked silicon sheets in today’s 2 nm chips, from tighter layouts, and from moving power wires to the back of the chip.

As a label, the name works. The trouble starts when we read it as a measurement or use it to compare one company with another.

Why this matters to me

As transistors shrink more slowly, more of the progress comes from how chips are put together, by stacking them and joining them with very fine copper connections. That is the part of the industry I study, and it has its own environmental cost, which I will write about in a later post.

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